1. Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming self-aligned silicide contacts on polysilicon gate field effect transistors.
2. Description of Prior Art
Complimentary metal oxide semiconductor(CMOS) field effect transistor(FET) technology involves the formation and utilization of n-channel FETs(NMOS) and p-channel FETs(PMOS) in combination to form low current, high performance integrated circuits. The complimentary use of NMOS and PMOS devices, typically in the form of a basic inverter device, allows a considerable increase of circuit density of circuit elements by reduction of heat generation. The increase in device density accompanied by the shrinkage of device size has resulted in improved circuit performance and reliability as well as reduced cost. For these reasons CMOS integrated circuits have found widespread use, particularly in digital applications.
One well known form of the CMOS configuration is the twin-well structure is shown in cross section by FIG. 1. By processes of photolithography and ion implantation, adjacent islands of p-type silicon 12 and n-type silicon 14 are formed in the surface of silicon wafer 10. Field oxide isolation(FOX) regions 16 are formed and gate oxide 18 is grown in the exposed silicon regions. A conductive layer of polysilicon is deposited and patterned to form the gate electrodes of the PMOS device 6 and the NMOS device 8. Using the gate electrodes 20 and 40 as a mask, the LDD (lightly doped drain) regions 24 and 44 are formed. The sidewalls 22 are next formed by anisotropically etching a blanket, conformally deposited mask material, for example silicon oxide. The sidewalls 22 protect the LDD regions 24,44 from a subsequent heavier dose source/drain ion implant which forms the source/drain regions 26 and 46. The formation of the PMOS device 6 and the NMOS device 8 is now complete. It is now necessary to form reliable ohmic contacts to the elements of the two MOSFETs as well as enhance the conductivity of the polysilicon gates.
A technique which has found widespread use in CMOS technology is the self-aligned silicide(SALICIDE) process. A layer of refractory metal, usually titanium is blanket deposited over the wafer 10. A thermal treatment, for example by rapid thermal annealing(RTA), causes the portions of the titanium in contact with silicon to react and form titanium silicide (TiSi.sub.2). Those portions of the titanium layer over oxide such as the field isolation 16 and the sidewall spacers 22 do not react, providing the temperature of the RTA is sufficiently low, for example around 650.degree. C. Referring now to FIG. 2, subsequent dissolution of the unreacted titanium using for example, an aqueous etchant containing H.sub.2 O.sub.2 and NH.sub.4 OH, leaves the TiSi.sub.2 28 and 48 over the source/drain regions 26 and 46 and also 29 and 49 over the polysilicon gate electrodes 20 and 40 respectively.
When the dimensions of the devices shrink into the sub half-micron range, problems begin to appear in this conventional process. In particular as the devices become smaller, so too do the sidewall spacers 22. Consequently, bridging of TiSi.sub.2 occurs between the source/drain regions and the polysilicon gate electrode. See Chang, C. Y. and Sze, S. M., "ULSI Technology" McGraw-Hill New York, (1996), p401.
The problem is further complicated by the fact that the thickness of the TiSi.sub.2 formed over the p-type regions of the PMOS devices is not the same as that which is formed over the n-type source/drains of the NMOS devices. This is because the reaction which forms TiSi.sub.2 on heavily doped silicon is dependent upon both the type and the concentration of impurities. This problem is has been pointed out by Mogami et.al. U.S. Pat. No. 5,571,735 who observes that the reaction forming TiSi.sub.2 is suppressed when the Ti is deposited over silicon having concentrations of arsenic greater than 5.times.10.sup.19 atoms/cm.sup.3. On the other hand TiSi.sub.2 is readily formed when the silicon upon which the Ti is deposited contains boron, arsenic in concentrations below 1.times.10.sup.19 atoms/cm.sup.3, or is undoped. It is therefore impossible to obtain metal silicide films of equal thickness when the titanium is deposited onto both heavily doped n- and p-type silicon surfaces as is the typical case in CMOS processing. Attempts at equalizing the thicknesses of TiSi.sub.2 grown on the PMOS and NMOS structures by a single arsenic implant have succeeded in reducing the gate-to-source drain bridging problem. However, the high dosage and energy required results in degradation of the PMOS devices.
Another problem which manifests itself at small geometries is the difficulty of achieving low resistance TiSi.sub.2 on narrow (&lt;0.5 micron) polysilicon lines. See Chang, C. Y. and Sze, S. M., "ULSI Technology" McGraw-Hill, New York, (1996), p402. This is caused by the increased difficulty in converting the C49 small grain high resistance TiSi.sub.2 crystalline phase to the C54 large grain low resistance crystalline phase by high temperature annealing. The structure consisting of a polysilicon layer and TiSi.sub.2 layer is commonly referred to as a polycide structure. Mogami et.al. reports that a TiSi.sub.2 film formed on polysilicon amorphisized by an arsenic implantation has a lower sheet resistance than TiSi.sub.2 films formed on non-amorphized silicon. Polycide lines in which the polysilicon layer was pre-amorphized with arsenic do not exhibit increasing resistance as line width decreases below 1 micron.
Pre-amorphization implantation(PAI) of single crystal silicon with Si.sup.+ and Ge.sup.+ ions has been used to prevent boron channeling in shallow junction PMOS devices (Wolf, S. and Tauber, R. N., "Silicon Processing for the VLSI Era", Vol. 1, Lattice Press, Sunset Beach, Calif., (1986), p294). The ions are implanted immediately prior to the boron dopant implantation. Naguib, et.al., U.S. Pat. No. 4,683,645 deposits a Ti layer for the formation of TiSi.sub.2 contacts and then implants Ge.sup.+ ions to affect mixing of the Ti and Si. Si.sup.+ ions are next implanted to amorphize the silicon to prevent boron channeling, followed by the implantation of the boron ions themselves. Kase, et.al., U.S. Pat. No. 5,145,794 cites the implantation of Si.sup.+ and Ge.sup.+ ions to pre-amorphize the silicon surface prior to the implantation of the boron dopant species BF.sub.2.sup.+. It was found that the high doses (10.sup.15 atoms/cm.sup.2) conventionally used to prevent boron channeling resulted in electrical degradation. Effective channeling reduction was achieved without electrical degradation by using reduced dosages of the order of 2-5.times.10.sup.13 atoms/cm.sup.2.
Ge and Si ions have also been found effective in facilitating the activation of impurity ions by amorphization. To this end Saito, U.S. Pat. No. 5,561,072 teaches a process of plasma implantation for forming very shallow junctions whereby the monocrystalline silicon substrate in the region of the plasma implantation is amorphized by introducing Si and Ge ions into the implantation plasma.
Pfiester, et.al., U.S. Pat. No. 4,835,112 implants germanium into the source/drain regions of MOSFETs after sidewall formation in a CMOS process. A salicide layer is then formed on the surface. Heavy doses of the n- and p-type dopants are then implanted through the salicide layer and into the subjacent silicon to form source/drain semiconductor elements. The Germanium serves to retard the diffusion of phosphorous. Aronowitz, et.al. U.S. Pat. No. 5,312,766 implant germanium into the source/drain regions of a MOSFET at a dose of 2.times.10.sup.16 atoms per cm.sup.2 and subject the wafer to a wet thermally oxidation whereupon the implanted germanium segregates to the surface to form a thin germanium rich layer. The layer then alloys with the contact metallurgy to form a low resistance contact.
Hefner, et.al. U.S. Pat. No. 5,254,484 cites an annealing method for recrystallizing silicon which has been amorphized by germanium or silicon implantation to retard impurity diffusion. Mader, et.al., U.S. Pat. No. 4,111,719 reports that the implantation of germanium reduces the occurrence of misfit dislocations formed in silicon, which has been heavily implanted with arsenic, during a subsequent high temperature drive-in step.